The present invention relates to a semiconductor device testing apparatus applicable to the burn-in test and the probe test, particularly suitable for the burn-in test in the wafer condition, so-called wafer level burn-in, and a method for manufacturing the same.
According to the inventors"" investigation regarding the techniques of the burn-in test in the tests and fabrication techniques of semiconductor integrated circuit devices, such techniques described in Japanese Patent Laid-Open Nos. 97494/1999 and 148389/1997, and xe2x80x9cNIKKEI MICRO-DEVICE, January 2000xe2x80x9d, pp. 148 to 153 are named.
Japanese Patent Laid-Open No. 97494/1999 discloses a technique that a pressing member is divided to equalize pressing in order to apply pressing load to a plurality of places in the surface of the pressing member, the surface is the opposite side of the surface facing to a wafer, when a plurality of probes formed in a membrane sheet is pressed onto the wafer with the pressing member in the burn-in test process.
Additionally, Japanese Patent Laid-Open No. 148389/1997 discloses a technique that a beam having vertical elasticity is formed of a silicon substrate by the micromachining technique and a micro-contact pin is formed on the tip end of the beam having conductive thin films deposited thereon so that the micro-contact pin faces and aligns with an electrode on a wafer.
Furthermore, xe2x80x9cNIKKEI MICRO-DEVICE, January 2000xe2x80x9d, describes a system using a TPS (Three Parts Structure) probe comprised of three components, a multilayer interconnection board, a thin film sheet with bumps and an anisotropic conductive rubber, and a system comprised of a multilayer interconnection board and a probe terminal having a structure of penetrating a copper post into a resin sheet in which the copper post is crushed to absorb height variations in electrodes when pressed.
In the meantime, as a result of investigating the techniques on the traditional burn-in test by the inventors, the following was revealed.
For example, as the test techniques of semiconductor integrated circuit devices, there are the burn-in test in which temperature and voltage stresses are applied in a high temperature atmosphere to screen chips likely to be defectives in future, and the probe test in which function tests to confirm whether a device operates as a predetermined function or DC and AC operating characteristics tests are performed to determine good/no-good products.
In recent years, in the burn-in test for semiconductor integrated circuit devices, the wafer-level burn-in technique of performing the burn-in test in a wafer condition has been used because of demands for a response to wafer shipment (quality differentiation), a response to KGD (Known Good Die) (yield improvements of MCP (Multi-Chip Package)), repair for defectives in the burn-in test, feedback of burn-in test defective data and reduction in total costs.
In this wafer level burn-in technique, a pressing mechanism for uniformly pressing the entire wafer surface, a wafer heating and temperature control mechanism, and ten thousands or more of probes throughout the wafer surface are needed.
Additionally, in the wafer level burn-in technique, warpage or waviness of a wafer and height variations in probes need to be absorbed, and thermal expansion at high temperatures also needs to be followed.
In the wafer level burn-in technique, required are routing many wires, focusing input signals, probe alignment throughout the wafer surface, separation of defective chips and breaking overcurrent, and contact check throughput the wafer surface.
On this account, in the wafer level burn-in technique, a problem has been arisen that test costs are increased because of a number of components required and a number of items to be adjusted.
Then, a technique for solving the problem regarding the burn-in test is the technique described in xe2x80x9cNIKKEI MICRO-DEVICE January 2000xe2x80x9d, for example.
However, the system using the TPS probe described in the reference needs a coating unit for eliminating defective chips and can implement wafer level burn-in only after the probe test or laser repair. Additionally, the thin film sheet with bumps has problems that it tends to increase contact resistance with the number of contact increased and is a one-piece product impossible in partial repair, and the anisotropic conductive rubber has a shorter lifetime.
Furthermore, the system using the multilayer interconnection board and the probe terminal, described in xe2x80x9cNIKKEI MICRO-DEVICE January 2000xe2x80x9d, the system has problems that the resin sheet is exclusive for a gold pad and disposable at every time.
For example, in the burn-in test or probe test, particularly in the wafer level burn-in test, the purpose of the invention is to realize a semiconductor device testing apparatus and a method for manufacturing the same, in which a divided contactor integration system is adapted, the divided contactors are positioned throughout the wafer surface highly accurately for uniform contact, whereby tests for a large-sized wafer is allowed to intend cost reduction.
To achieve the purpose described above, the invention is configured as follows:
(1) In a semiconductor device testing apparatus comprising a contactor substrate having a probe for electrically contacting a plurality of electrode pads in a semiconductor device, the contactor substrate has a plurality of contactor blocks, each of the contactor blocks is formed with the probe formed in a beam, wiring and a positioning notch part, and a positioning frame for positioning the plurality of contactor blocks is disposed, the positioning frame is formed with a supporting part for supporting the positioning notch part formed in the contactor block.
(2) Preferably, in item (1), the positioning notch part formed in the contactor block is a positioning groove formed in the contactor block, and the positioning groove is formed in a probe forming surface of the contactor block.
(3) Also preferably in item (2), the positioning groove in the contactor block is two groves almost orthogonal each other.
(4) Furthermore, in items (1), (2) and (3), the contactor blockpreferably has silicon in the material thereof.
(5) Moreover, in items (1), (2), (3) and (4), the positioning frame has 42 alloy, nickel alloy, glass, or silicon in the material thereof.
(6) In a contactor substrate for use in a semiconductor device testing apparatus, which has a probe for electrically contacting a plurality of electrode pads in a semiconductor device, the contactor substrate has a plurality of contactor blocks, each of the contactor blocks is formed with the probe formed in a beam, wiring and a positioning notch part, in which a positioning frame for positioning the plurality of contactor blocks performs positioning, the positioning frame is formed with a supporting part for supporting the positioning notch part formed in the contactor block.
(7) In a method for manufacturing a semiconductor device testing apparatus in which a contactor substrate has a probe for electrically contacting a plurality of electrode pads, the contactor substrate has a plurality of contactor blocks wherein each of the contactor blocks is formed with the probe formed in a beam, wiring and a positioning notch part, the method comprising the steps of: depositing a thermally-oxidized film over a substrate surface to form a mask pattern for forming the probe; forming the probe according to etching processing; forming a multilayer mask; processing holes having a different depth by etching to process the beam, a through hole, and a positioning step part; and depositing a metal thin film on both sides for patterning to form a wiring layer, whereby the contactor block is formed.
According to the semiconductor device testing apparatus of the invention, the contactor substrate can be positioned in the X- and Y-directions and also the Z-direction of the height direction. Furthermore, an amount of relative shift in alignment caused by the difference of a linear expansion coefficient due to temperature rise becomes greater in the peripheral part as compared with a system of positioning the contactor substrate at end faces. However, positioning can be done in the center part of the divided contactors in the invention. Thus, it is hardly subject to the influence of the amount of relative shift in alignment caused by the difference of a linear expansion coefficient due to temperature rise in the positioning frame. In other words, the influence of shift in alignment between probes and electrode pads formed on a wafer to be tested is significantly small in a large-sized wafer to be tested as well.
A plurality of divided contactor blocks is independent of the size of a wafer to be tested. Therefore, traditional facilities can be utilized for wafers increasing in size. Accordingly, fabrication costs of the contactor substrate according to a wafer full surface simultaneous contact system can be reduced.
Moreover, positioning in the X-, Y- and Z-directions is allowed as well, and thus the contactor substrate is allowed to follow warpage or waviness of the wafer to be tested independently.
Besides, the wafer to be tested and the contactor blocks are expanded similarly under temperature conditions during the burn-in test. Therefore, the alignment accuracy of the probes can be obtained sufficiently throughout the wafer surface.